ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 296
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ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A1-AU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATxmega64A1U-AU
Manufacturer:
ATMEL
Quantity:
953
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25.7
25.8
25.9
8077H–AVR–12/09
Compare function
Starting a conversion
ADC Clock and Conversion Timing
Figure 25-11. Unsigned single ended and internal input, input range, and result representation
The ADC has a built in 12-bit compare function. The ADC compare register can hold a 12-bit
value that represent an analog threshold voltage. Each ADC Channel can be configured to auto-
matically compare its result with this 12-bit compare value to give an interrupt or event only
when the result is above or below the threshold.
All four ADC Channels share the same compare register.
Before a conversion is started, the desired input source must be selected for one or more ADC
channels. An ADC conversion for a ADC channel can either be started by the application soft-
ware writing to the start conversion bit for the ADC channel, or from any of the events in the
Event System. It is possible to write the start conversion bit for several ADC channels at the
same time, or to use one event to trigger conversions on several ADC channels at the same
time. Using this it is possible to scan several or all ADC channels from one event.
The ADC is clocked from the Peripheral Clock. The ADC can prescale the Peripheral Clock to
provide an ADC Clock (Clk
Figure 25-12. ADC Prescaler
The maximum ADC sample rate is given by the he ADC clock frequency (f
sample a new measurement on every ADC clock cycle.
The propagation delay of an ADC measurement is given by:
Sample Rate
VREF
GND
−
Δ
V
=
f
ADC
PRESCALER[2:0]
ADC
Clk
) that is within the minimum and maximum frequency for the ADC.
PER
VINN
=
VREF
2
VINP
−
Δ
9-bit ADC Prescaler
V
4095
4094
4093
Dec
203
202
201
200
...
...
0
Clk
FFD
0CB
0CA
Hex
FFF
FFE
0C9
0C8
...
ADC
0
1111 1111 1111
1111 1111 1110
1111 1111 1101
0000 1100 1011
0000 1100 1010
0000 1100 1001
0000 1100 1000
0000 0000 0000
Binary
...
0000 1111 1111 1111
0000 1111 1111 1110
0000 1111 1111 1101
0000 0000 1100 1011
0000 0000 1100 1010
0000 0000 1100 1001
0000 0000 1100 1000
0000 0000 0000 0000
16-bit result register
ADC
XMEGA A
). The ADC can
...
296
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