ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 303
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ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Price
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Part Number:
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25.16.3
8077H–AVR–12/09
REFCTRL - ADC Reference Control register
• Bit 4 - CONVMODE: ADC Conversion Mode
This bit controls whether the ADC should work in signed or unsigned mode. By default this bit is
zero and the ADC is then configured for unsigned mode where single ended and internal signals
can be measured. When this bit is set to one the ADC is configured for signed mode where also
differential input can be used.
• Bit 3 - FREERUN: ADC Free Running Mode
This bit controls the free running mode for the ADC. When the bit is set to one the ADC channels
defined in the EVCTRL register are swept repeatedly.
• Bits 2:1 - RESOLUTION[1:0]: ADC Conversion Result Resolution
These bits define whether the ADC completes the conversion at 12- or 8-bit result. They also
define whether the 12-bit result is left or right oriented in the 16-bit result registers. See
25-2 on page 303
Table 25-2.
• Bit 0 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
Note:
• Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 6:4 – REFSEL[1:0]: ADC Reference Selection
These bits selects the reference and conversion range for the ADC according to
page
Bit
+0x02
Read/Write
Initial Value
RESOLUTION[1:0]
304.
1. Refer to datasheet for limitations on reference voltage.
00
01
10
11
R
7
0
-
ADC Conversion Result resolution
for possible settings.
R
6
0
-
Group Configuration
(1)
R/W
LEFT12BIT
5
0
REFSEL[1:0]
12BIT
8BIT
R/W
4
0
R
3
0
-
Description
12-bit result, right adjusted
Reserved
8-bit result, right adjusted
12-bit result, left adjusted
R
2
0
-
BANDGAP
R/W
1
0
XMEGA A
TEMPREF
R/W
0
0
Table 25-3 on
REFCTRL
Table
303
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