SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 103
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 103 of 290
- Download datasheet (5Mb)
4.10.2
ARM DDI 0165B
Data interface, sequential cycles
If you are designing a memory controller for the ARM9E-S, and your memory system
is unable to cope with this case, use the CLKEN signal to extend the bus cycle to allow
sufficient cycles for the memory system (see Use of CLKEN to control bus cycles on
page 4-31).
Sequential cycles perform burst transfers on the bus. You can use this information to
optimize the design of a memory controller interfacing to a burst memory device, such
as a DRAM.
During a sequential cycle, the ARM9E-S requests a memory location that is part of a
sequential burst. If this is the first cycle in the burst, the address can be the same as the
previous internal cycle. Otherwise the address is incremented from the previous cycle.
For a burst of word accesses, the address is incremented by 4 bytes.
Bursts of halfword or byte accesses are not possible on the ARM9E-S data interface.
A burst always starts with an N cycle and continues with S cycles. A burst comprises
transfers of the same type. The DA[31:0] signal increments during the burst. The other
address class signals are unaffected by a burst.
CLK
Address class
signals
DnRW
DnMREQ,
DSEQ,
DMORE
WDATA[31:0]
(Write)
RDATA[31:0]
(Read)
Copyright © 2000 ARM Limited. All rights reserved.
Write address
N cycle
Write cycle
Figure 4-10 Back to back memory cycles
Read address
Write data
N cycle
Read cycle
Read data
Memory Interface
4-27
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