SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 96
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 96 of 290
- Download datasheet (5Mb)
Memory Interface
4-20
Figure 4-6 shows the ARM9E-S behavior for an aborted STR instruction followed by
an LDM instruction. While the STR instruction is canceled, a memory request is made
in the first cycle of the LDM before the Data Abort exception is taken.
For more details about aborts, see Aborts on page 2-23.
Copyright © 2000 ARM Limited. All rights reserved.
CLK
DnRW
DnMREQ
DSEQ
DMORE
DABORT
Address class
signals
WDATA[31:0]
(Write)
Figure 4-6 ARM9E-S aborted data memory access
Write address
Write cycle
(aborted)
Read address
Write data
memory system)
(ignored by
Read cycle
ARM DDI 0165B
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