SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 60
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SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 60 of 290
- Download datasheet (5Mb)
Programmer’s Model
2-18
M[4:0]
10000
10001
10010
10011
10111
11011
11111
a. Access to these registers is limited in Thumb state.
Mode
User
FIQ
IRQ
Supervisor
Abort
Undefined
System
Visible Thumb state registers
r0–r7, r8-r12
r0–r7, r8_fiq-r12_fiq
CPSR, SPSR_fiq
r0–r7, r8-r12
SPSR_irq
r0–r7, r8-r12
SPSR_svc
r0–r7, r8-r12
SPSR_abt
r0–r7, r8-r12
SPSR_und
r0–r7, r8-r12
The T bit reflects the operating state:
•
•
The operating state is reflected by the ITBIT external signal.
Mode bits
The M4, M3, M2, M1, and M0 bits (M[4:0]) are the mode bits. These bits determine the
processor operating mode as shown in Table 2-2.
An illegal value programmed into M[4:0] causes the processor to enter an
unrecoverable state. If this occurs, apply reset.
Not all combinations of the mode bits define a valid processor mode, so take care to use
only those bit combinations shown.
when the T bit is set, the processor is executing in Thumb state
when the T bit is clear, the processor is executing in ARM state.
Caution
Copyright © 2000 ARM Limited. All rights reserved.
a
a
a
a
a
a
, SP, LR, PC, CPSR
, SP_irq, LR_irq, PC, CPSR,
, SP_svc, LR_svc, PC, CPSR,
, SP_abt, LR_abt, PC, CPSR,
, SP_und, LR_und, PC, CPSR,
, SP, LR, PC, CPSR
a
, SP_fiq, LR_fiq PC,
Visible ARM state registers
r0–r14, PC, CPSR
r0–r7, r8_fiq–r14_fiq, PC, CPSR, SPSR_fiq
r0–r12, r13_irq, r14_irq, PC, CPSR, SPSR_irq
r0–r12, r13_svc, r14_svc, PC, CPSR,
SPSR_svc
r0–r12, r13_abt, r14_abt, PC, CPSR,
SPSR_abt
r0–r12, r13_und, r14_und, PC, CPSR,
SPSR_und
r0–r14, PC, CPSR
Table 2-2 PSR mode bit values
ARM DDI 0165B
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