SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 204
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 204 of 290
- Download datasheet (5Mb)
Instruction Cycle Times
8.26
8-44
Cycle
ready
not ready
a. IREQ = InMREQ, ISEQ.
b. DREQ = DnMREQ, DSEQ.
c. P = PASS.
d. LC = LATECANCEL.
Double coprocessor register transfer (to ARM)
1
2
1
.
n
n+1
n+2
IA
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
The move double from coprocessor (
registers into the specified ARM registers.
Data is transferred over the data bus interface, in a similar fashion to a load register
operation.
An interrupt can cause the ARM9E-S to abandon a busy-waiting coprocessor
instruction (see Busy-waiting and interrupts on page 6-17).
Coprocessor operations are only available in ARM state.
The
MRRC
IREQ
I cycle
S cycle
I cycle
I cycle
I cycle
I cycle
S cycle
Note
Copyright © 2000 ARM Limited. All rights reserved.
instruction cycle timings are shown in Table 8-33.
a
INSTR
(pc+2i)
-
(pc+3i)
(pc+2i)
-
-
-
-
(pc+3i)
DA
-
-
-
-
-
-
-
DREQ
C cycle
C cycle
I cycle
I cycle
I cycle
C cycle
C cycle
MRRC
b
) operation transfers two coprocessor
Table 8-33 MRRC instruction cycle timing
RDATA
CPData1
CPData2
-
-
-
CPData1
CPData2
P
1
1
1
1
1
1
1
c
LC
0
0
0
0
0
0
0
d
CHSD
GO
WAIT
ARM DDI 0165B
CHSE
LAST
-
WAIT
WAIT
GO
LAST
-
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