SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 151
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 151 of 290
- Download datasheet (5Mb)
7.5.4
7.5.5
7.5.6
ARM DDI 0165B
Watchpoints and exceptions
Debug request
Actions of the ARM9E-S in debug state
If there is an abort with the data access as well as a watchpoint, the watchpoint condition
is latched, the exception entry sequence is performed, and then the processor enters
debug state. If there is an interrupt pending, the ARM9E-S allows the exception entry
sequence to occur and then enters debug state.
A debug request can take place through the EmbeddedICE-RT logic or by asserting the
EDBGRQ signal. The request is registered and passed to the processor. Debug request
takes priority over any pending interrupt. Following registering, the core enters debug
state when the instruction at the Execute stage of the pipeline has completely finished
executing (once Memory and Write stages of the pipeline have completed). While
waiting for the instruction to finish executing, no more instructions are issued to the
Execute stage of the pipeline.
When a debug request occurs, the ARM9E-S enters debug state even if the
EmbeddedICE-RT is configured for monitor mode debug.
Once the ARM9E-S is in debug state, both memory interfaces indicate internal cycles.
This allows the rest of the memory system to ignore the ARM9E-S and function as
normal. Because the rest of the system continues operation, the ARM9E-S ignores
aborts and interrupts.
The CFGBIGEND signal must not be changed by the system while in debug state. If it
changes, not only is there a synchronization problem, but the view of the ARM9E-S
seen by the programmer changes without the knowledge of the debugger. The nRESET
signal must also be held stable during debug. If the system applies reset to the
ARM9E-S (nRESET is driven LOW), the state of the ARM9E-S changes without the
knowledge of the debugger.
Copyright © 2000 ARM Limited. All rights reserved.
Debug Interface and EmbeddedICE-RT
7-13
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