SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 196
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 196 of 290
- Download datasheet (5Mb)
Instruction Cycle Times
8.20
8-36
Cycle
1
2
3
Software interrupt, undefined instruction, and exception entry
IA
Xn
Xn+4
Xn+8
InMREQ,
ISEQ
N cycle
S cycle
S cycle
Exceptions, software interrupts (SWIs), and undefined instructions force the PC to a
specific value and refill the instruction pipeline from this address:
1.
2.
3.
The exception entry cycle timings are show in Table 8-27, where:
pc
Xn
The value on the INSTR bus can be unpredictable in the case of Prefetch Abort or Data
Abort entry.
During the first cycle, the ARM9E-S constructs the forced address, and a mode
change might take place.
During the second cycle, the ARM9E-S performs a fetch from the exception
address. The return address to be stored in r14 is calculated. The state of the CPSR
is saved in the relevant SPSR.
During the third cycle, the ARM9E-S performs a fetch from the exception address
+ 4, refilling the instruction pipeline.
Note
Copyright © 2000 ARM Limited. All rights reserved.
InTRANS
1
1
1
Is one of:
•
•
•
•
Is the appropriate exception address.
the address of the
the address of the instruction following the last one to be executed
before entering the exception for interrupts
the address of the aborted instruction for Prefetch Aborts
the address of the instruction following the one that attempted the
aborted data transfer for Data Aborts.
ITBIT
0
0
0
SWI
INSTR
(Xn)
(Xn+4)
(Xn+8)
instruction for SWIs
Table 8-27 Exception entry cycle timing
DA
-
-
-
DnMREQ,
DSEQ
I cycle
I cycle
I cycle
ARM DDI 0165B
RDATA/
WDATA
-
-
-
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