SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 172
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SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 172 of 290
- Download datasheet (5Mb)
Instruction Cycle Times
8.7
8-12
Data operations
A normal data operation executes in a single execute cycle except where the shift is
determined by the contents of a register. A normal data operation requires up to two
operands, that are read from the register file onto the A and B buses.
The ALU combines the A bus operand with the (shifted) B bus operand according to
the operation specified in the instruction. The ARM9E-S pipelines this result and writes
it into the destination register, when required. Compare and test operations do not write
a result as they only affect the status flags.
An instruction prefetch occurs at the same time as the data operation, and the PC is
incremented.
When a register specified shift is used, an additional execute cycle is needed to read the
shifting register operand. The instruction prefetch occurs during this first cycle.
The PC can be one or more of the register operands. When the PC is the destination, the
external bus activity is affected. When the ARM9E-S writes the result to the PC, the
contents of the instruction pipeline are invalidated, and the ARM9E-S takes the address
for the next instruction prefetch from the ALU rather than the incremented address. The
ARM9E-S refills the instruction pipeline before any further instruction execution takes
place. Exceptions are locked out while the pipeline is refilling.
Shifted register with destination equals PC is not possible in Thumb state.
The data operation cycle timings are shown in Table 8-8.
Cycle
Normal
dest=pc
Note
Copyright © 2000 ARM Limited. All rights reserved.
1
1
2
3
pc+3i
IA
pc’
pc’+ i
pc’+2i
InMREQ,
ISEQ
S cycle
N cycle
S cycle
S cycle
INSTR
(pc+2i)
(pc+3i)
(pc+2i)
(pc’)
(pc’+i)
(pc’+ 2i)
Table 8-8 Data operation cycle timing
DA
-
-
-
-
DnMREQ,
DSEQ
I cycle
I cycle
I cycle
I cycle
ARM DDI 0165B
RDATA/
WDATA
-
-
-
-
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