STM32W108CC STMicroelectronics, STM32W108CC Datasheet - Page 106

• Manufacturer Part Number: STM32W108CC
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CC

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

Serial interfaces
9.13.2
Table 69.
106/232
31
15
Reserved
Bits [12:10] SC_RXSSEL: Status of the receive count saved in SCx_RXCNTSAVED (SPI slave mode)
30
14
Serial DMA status register (SCx_DMASTAT)
Address offset: 0xC82C (SC1_DMASTAT) and 0xC02C (SC2_DMASTAT)
Reset value:
Serial DMA status register (SCx_DMASTAT)
Bit 9 SC_RXFRMB: This bit is set when DMA receive buffer B reads a byte with a frame error from
Bit 8 SC_RXFRMA: This bit is set when DMA receive buffer A reads a byte with a frame error from
Bit 7 This bit is set when DMA receive buffer B reads a byte with a parity error from the receive FIFO.
Bit 6 This bit is set when DMA receive buffer A reads a byte with a parity error from the receive FIFO.
Bit 5 This bit is set when DMA receive buffer B was passed an overrun error from the receive FIFO.
Bit 4 This bit is set when DMA receive buffer A was passed an overrun error from the receive FIFO.
Bit 3 This bit is set when DMA transmit buffer B is active.
29
13
when nSSEL deasserts. Cleared when a receive buffer is loaded and when the receive DMA is
reset.
the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset.
(SC1 in UART mode only)
the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset.
(SC1 in UART mode only)
It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1 in UART
mode only)
It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1 in UART
mode only)
Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled
up. Buffer B was the next buffer to load, and when it drained the FIFO the overrun error was
passed up to the DMA and flagged with this bit. Cleared the next time buffer B is loaded and
when the receive DMA is reset.
Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled
up. Buffer A was the next buffer to load, and when it drained the FIFO the overrun error was
passed up to the DMA and flagged with this bit. Cleared the next time buffer A is loaded and
when the receive DMA is reset.
0: No count was saved because nSSEL did not deassert.
2: Buffer A's count was saved, nSSEL deasserted once.
3: Buffer B's count was saved, nSSEL deasserted once.
6: Buffer A's count was saved, nSSEL deasserted more than once.
7: Buffer B's count was saved, nSSEL deasserted more than once.
1, 4, 5: Reserved.
28
12
SC_RXSSEL
27
11
r
0x0000 0000
26
10
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
SC_RX
FRMB
25
9
r
Doc ID 16252 Rev 13
SC_RX
FRMA
24
8
r
Reserved
SC_RX
PARB
23
7
r
SC_RX
PARA
22
6
r
SC_RX
OVFB
21
5
r
SC_R
XOVF
20
A
4
r
SC_TX
ACTB
19
3
r
SC_TX
ACTA
18
2
r
SC_RX
ACTB
17
1
r
SC_RX
ACTA
16
0
r