STM32W108CC STMicroelectronics, STM32W108CC Datasheet - Page 43

• Manufacturer Part Number: STM32W108CC
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CC

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
6.3.5
6.3.6
Table 7.
31
15
30
14
Clock switching
The STM32W108 has two switching mechanisms for the main system clock, providing four
clock modes.
The register bit OSC24M_SEL in the OSC24M_CTRL register switches between the high-
frequency RC oscillator (OSCHF) and the high-frequency crystal oscillator (OSC24M) as
the main system clock (SCLK). The peripheral clock (PCLK) is always half the frequency of
SCLK.
The register bit CPU_CLK_SEL in the CPU_CLKSEL register switches between PCLK and
SCLK to produce the ARM® Cortex-M3 CPU clock (FCLK). The default and preferred mode
of operation is to run the CPU at the lower PCLK frequency, 12 MHz, but the higher SCLK
frequency, 24 MHz, can be selected to give higher processing performance at the expense
of an increase in power consumption.
In addition to these modes, further automatic control is invoked by hardware when flash
programming is enabled. To ensure accuracy of the flash controller's timers, the FCLK
frequency is forced to 12 MHz during flash programming and erase operations.
Table 6.
Clock switching registers
XTAL or OSCHF main clock select register (OSC24M_CTRL)
Address offset: 0x4000 401C
Reset value: 0x0000 0000
XTAL or OSCHF main clock select register (OSC24M_CTRL)
Bit 1
Bit 0
OSC24M_SEL
1 (OSC24M)
1 (OSC24M)
29
13
0 (OSCHF)
0 (OSCHF)
OSC24M_EN: When set to ‘1’, 24 MHz crystal oscillator is main clock.
OSC24M_SEL: When set to ‘0’, OSCHF is selected. When set to ‘1’, XTAL is selected.
28
12
System clock modes
27
11
CPU_CLK_SEL
0 (Normal CPU)
0 (Normal CPU)
1 (Fast CPU)
1 (Fast CPU)
26
10
25
9
Reserved
Doc ID 16252 Rev 13
24
8
12 MHz
12 MHz
24 MHz
24 MHz
Reserved
SCLK
23
7
22
6
12 MHz
12 MHz
6 MHz
6 MHz
PCLK
21
5
20
Erase Inactive
4
Program/
12 MHz
12 MHz
24 MHz
6 MHz
Flash
19
3
System modules
f
18
CLK
2
Erase Active
Program/
OSC24
M_EN
12 MHz
12 MHz
12 MHz
12 MHz
rws
Flash
17
1
43/232
OSC24
M_SEL
rws
16
0