STM32W108CC STMicroelectronics, STM32W108CC Datasheet - Page 45

• Manufacturer Part Number: STM32W108CC
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CC

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
6.4.2
6.4.3
6.4.4
Sleep timer
The STM32W108 integrates a 32-bit timer dedicated to system timing and waking from
sleep at specific times. The sleep timer can use either the calibrated 1 kHz
reference(CLK1K), or the 32 kHz crystal clock (CLK32K). The default clock source is the
internal 1 kHz clock. The sleep timer clock source is chosen with the SLEEPTMR_CLKSEL
register.
The sleep timer has a prescaler, a divider of the form 2^N, where N can be programmed
from 1 to 2^15. This divider allows for very long periods of sleep to be timed. The timer
provides two compare outputs and wrap detection, all of which can be used to generate an
interrupt or a wake up event.
The sleep timer is paused when the debugger halts the ARM® Cortex-M3. No additional
register bit must be set.
To save current during deep sleep, the low-frequency internal RC oscillator (OSCRC) can
be turned off. If OSCRC is turned off during deep sleep and a low-frequency 32.768 kHz
crystal oscillator is not being used, then the sleep timer will not operate during deep sleep
and sleep timer wake events cannot be used to wakeup the STM32W108.
Event timer
The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can
be clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer clock.
FCLK is either the SCLK or PCLK as selected by CPU_CLK_SEL (see
switching on page
Slow timers (Watchdog and Sleeptimer) control and status registers
These registers are powered from the always-on power domain.
All registers are only writable when in System mode
Watchdog general control register (WDOG_CFG)
Register bits for general top level chip functions and protection.
Watchdog bits can only be written after first writing the appropriate code to the
WDOG_CTRL register.
Address:
Reset value:
0x4000 6000
0x0000 0002
43).
Doc ID 16252 Rev 13
Section 6.3.5: Clock
System modules
45/232