STM32W108CC STMicroelectronics, STM32W108CC Datasheet - Page 188

• Manufacturer Part Number: STM32W108CC
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CC

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

Interrupts
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Table 123. NVIC exception table (continued)
The NVIC also contains a software-configurable interrupt prioritization mechanism. The
Reset, NMI, and Hard Fault exceptions, in that order, are always the highest priority, and are
not software-configurable. All other exceptions can be assigned a 5-bit priority number, with
low values representing higher priority. If any exceptions have the same software-
configurable priority, then the NVIC uses the hardware-defined priority. The hardware-
defined priority number is the same as the position of the exception in the exception table.
For example, if IRQA and IRQB both fire at the same time and have the same software-
defined priority, the NVIC handles IRQA, with priority number 28, first because it has a
higher hardware priority than IRQB with priority number 29.
The top level interrupts are controlled through five ARM® Cortex-M3 NVIC registers:
INT_CFGSET, INT_CFGCLR, INT_PENDSET, INT_PENDCLR, and INT_ACTIVE. Writing 0
into any bit in any of these five register is ineffectual.
●
●
●
●
●
INT_PENDSET and INT_PENDCLR set and clear a simple latch; INT_CFGSET and
INT_CFGCLR set and clear a mask on the output of the latch. Interrupts may be pended
and cleared at any time, but any pended interrupt will not be taken unless the corresponding
mask (INT_CFGSET) is set, which allows that interrupt to propagate. If an INT_CFGSET bit
is set and the corresponding INT_PENDSET bit is set, then the interrupt will propagate and
be taken. If INT_CFGSET is set after INT_PENDSET is set, then the interrupt will also
propagate and be taken. Interrupt flags (signals) from the top level interrupts are level-
sensitive.
The second-level interrupt registers, which provide control of the second-level Event
Manager peripheral interrupts, are described in
For further information on the NVIC and Cortex-M3 exceptions, refer to the ARM® Cortex-
M3 Technical Reference Manual and the ARM ARMv7-M Architecture Reference Manual.
Exception
INT_CFGSET - Writing 1 to a bit in INT_CFGSET enables that top level interrupt.
INT_CFGCLR - Writing 1 to a bit in INT_CFGCLR disables that top level interrupt.
INT_PENDSET - Writing 1 to a bit in INT_PENDSET triggers that top level interrupt.
INT_PENDCLR - Writing 1 to a bit in INT_PENDCLR clear that top level interrupt.
INT_ACTIVE cannot be written to and is used for indicating which interrupts are
currently active.
Debug
IRQD
Position
31
32
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
IRQD peripheral interrupt.
Debug peripheral interrupt.
Doc ID 16252 Rev 13
Section 12.2: Event
Description
manager.