STM32W108CC STMicroelectronics, STM32W108CC Datasheet - Page 170

• Manufacturer Part Number: STM32W108CC
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CC

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

General-purpose timers
10.3.17
Table 104. Timer x interrupt configuration register (INT_TIMxCFG)
10.3.18
Table 105. Timer x interrupt flag register (INT_TIMxFLAG)
170/232
31
15
31
15
Reserved
30
14
30
14
Bits [12:9]
Timer x interrupt configuration register (INT_TIMxCFG)
Address offset: 0xA840 (TIM1) and 0xA844 (TIM2)
Reset value:
Timer x interrupt flag register (INT_TIMxFLAG)
Address offset: 0xA800 (TIM1) and 0xA804 (TIM2)
Reset value:
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
29
13
29
13
INT_TIMTIF: Trigger interrupt enable.
INT_TIMCC4IF: Capture or compare 4 interrupt enable.
INT_TIMCC3IF: Capture or compare 3 interrupt enable.
INT_TIMCC2IF: Capture or compare 2 interrupt enable.
INT_TIMCC1IF: Capture or compare 1 interrupt enable.
INT_TIMUIF: Update interrupt enable.
INT_TIMRSVD: May change during normal operation.
INT_TIMTIF: Trigger interrupt.
INT_TIMCC4IF: Capture or compare 4 interrupt pending.
INT_TIMCC3IF: Capture or compare 3 interrupt pending.
INT_TIMCC2IF: Capture or compare 2 interrupt pending.
INT_TIMCC1IF: Capture or compare 1 interrupt pending.
INT_TIMUIF: Update interrupt pending.
28
12
28
12
Reserved
INT_TIMRSVD
27
11
27
11
0x0000 0000
0x0000 0000
r
26
10
26
10
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
25
25
9
9
Doc ID 16252 Rev 13
24
24
8
8
Reserved
Reserved
Reserved
23
23
7
7
INT_TI
INT_TI
MTIF
MTIF
22
22
rw
rw
6
6
Reserv
Reserv
21
ed
21
ed
5
5
INT_T
INT_T
IMCC
IMCC
4IF
4IF
20
rw
20
rw
4
4
MCC3I
MCC3I
INT_TI
INT_TI
19
rw
19
rw
3
F
3
F
MCC2I
MCC2I
INT_TI
INT_TI
18
18
rw
rw
2
F
2
F
MCC1I
MCC1I
INT_TI
INT_TI
17
17
rw
rw
1
F
1
F
INT_TI
INT_TI
MUIF
MUIF
16
rw
16
rw
0
0