STM32W108CC STMicroelectronics, STM32W108CC Datasheet - Page 118

• Manufacturer Part Number: STM32W108CC
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CC

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

General-purpose timers
Note:
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The auto-reload register is buffered. Writing to or reading from the auto-reload register
accesses the buffer register. The contents of the buffer register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
buffer enable bit (TIM_ARBE) in the TIMx_CR1 register. The update event is generated
when both the counter reaches the overflow (or underflow when down-counting) and when
the TIM_UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software.
Update event generation is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (TIM_CEN) in the TIMx_CR1 register is set. Refer also to the slave mode
controller description in the Timers and External Trigger Synchronization section to get more
details on counter enabling.
Note that the actual counter enable signal CNT_EN is set one clock cycle after TIM_CEN.
When the STM32W108 enters debug mode and the ARM® Cortex-M3 core is halted, the
counters continue to run normally.
Prescaler
The prescaler can divide the counter clock frequency by power of two from 1 through 32768.
It is based on a 16-bit counter controlled through the 4-bit TIM_PSCEXP bit field in the
TIMx_PSC register. The factor by which the counter is divided is two raised to the power
TIM_PSCEXP (2TIM_PSCEXP).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
used starting at the next update event.
Figure 16
the fly.
Figure 16. Counter timing diagram with prescaler division change from 1 to 4
gives an example of the counter behavior when the prescaler ratio is changed on
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Doc ID 16252 Rev 13