ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 146

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ST72561J9-Auto

Manufacturer Part Number
ST72561J9-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72561J9-Auto

Hdflash Endurance
100 cycles, data retention 20 years at 55 °C
5 Power Saving Modes
halt, auto wake up from halt, active halt, wait and slow
Serial peripheral interface (SPI)
14.3.1
146/324
Figure 70. Serial peripheral interface block diagram
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see
slave must be programmed with the same timing mode.
MOSI
MISO
SCK
SS
Figure
SOD
bit
71.
SPIDR
8-Bit Shift Register
Read Buffer
SERIAL CLOCK
GENERATOR
CONTROL
Doc ID 12370 Rev 8
MASTER
Data/Address Bus
Read
Write
7
SPIE
SPIF WCOL
7
SPE
CONTROL
SPR2
OVR
STATE
SPI
Interrupt
request
MODF
MSTR
Figure
CPOL
0
CPHA
SOD
74) but master and
SS
SPICR
SPICSR
SSM
SPR1
ST72561-Auto
0
1
SPR0
SSI
0
0

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