ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 197

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ST72561J9-Auto

Manufacturer Part Number
ST72561J9-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72561J9-Auto

Hdflash Endurance
100 cycles, data retention 20 years at 55 °C
5 Power Saving Modes
halt, auto wake up from halt, active halt, wait and slow
ST72561-Auto
16.4
Figure 88. SCI block diagram
Functional description
The block diagram of the serial control interface, is shown in
dedicated registers:
SCLK
TDO
RDI
Three control registers (SCICR1, SCICR2 and SCICR3)
A status register (SCISR)
A baud rate register (SCIBRR)
An extended prescaler receiver register (SCIERPR)
An extended prescaler transmitter register (SCIETPR)
TIE
SCICR2
TRANSMITTER
INTERRUPT
CLOCK EXTRACTION
PHASE AND POLARITY
TCIE
CONTROL
CLOCK
f
CPU
Transmit Data Register (TDR)
SCI
TRANSMIT
CONTROL
CONTROL
RIE
Transmit Shift Register
Write
ILIE
/16
TE
Doc ID 12370 Rev 8
LINSCI serial communication interface (LIN master only)
RE
/PR
RWU
WAKE
UNIT
UP
R8
SBK
LINE
T8
CONVENTIONAL BAUD RATE GENERATOR
SCP1
Received Data Register (RDR)
SCID
Read
-
SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
Received Shift Register
TDRE TC RDRF IDLE OR
TRANSMITTER RATE
-
M
CONTROL
CLKEN
WAKE
RECEIVER
CONTROL
CPOL CPHA LBCL
(DATA REGISTER) SCIDR
PCE
RECEIVER RATE
CONTROL
Figure
PS
PIE
SCIBRR
88. It contains seven
NF
SCICR3
SCICR1
RECEIVER
FE
CLOCK
SCISR
PE
197/324

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