ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 206

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ST72561J9-Auto

Manufacturer Part Number
ST72561J9-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72561J9-Auto

Hdflash Endurance
100 cycles, data retention 20 years at 55 °C
5 Power Saving Modes
halt, auto wake up from halt, active halt, wait and slow
LINSCI serial communication interface (LIN master only)
Note:
206/324
The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled
(TE and RE = 0), the SCLK and TDO pins go into high impedance state.
The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter to
ensure that the clock pulses function correctly. These bits should not be changed while the
transmitter is enabled.
Figure 91. SCI example of synchronous and asynchronous transmission
Figure 92. SCI data clock timing diagram (M = 0)
Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Idle or preceding
transmission
Data
SCI
Output port
Start
Start
SCLK
TDO
RDI
Doc ID 12370 Rev 8
LSB
0
1
M = 0 (8 data bits)
Data out
Data in
Data in
Clock
Enable
2
3
4
Asynchronous
(e.g. modem)
Synchronous
(e.g. shift register)
5
* LBCL bit controls last data clock pulse
6
MSB Stop
*
*
7
*
*
Stop
Idle or next
transmission
ST72561-Auto

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