ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 264

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

Instruction set
19
19.1
264/324
Instruction set
CPU addressing modes
The CPU features 17 different addressing modes which can be classified in seven main
groups:
Table 94.
The CPU Instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be subdivided in two submodes
called long and short:
●
●
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 95.
Inherent
Immediate
Direct
Indexed
Indirect
Relative
Bit operation
Inherent
Immediate
Short
Long
No Offset
Short
Long
Short
Long
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Mode
Direct
Direct
Direct
Direct
Direct
Indirect
Indirect
Addressing mode groups
CPU addressing mode overview
Addressing mode
Indexed ld A, (X)
Indexed ld A, ($10,X)
Indexed ld A, ($1000,X)
nop
ld A, #$55
ld A, $10
ld A, $1000
ld A, [$10]
ld A, [$10.w]
Doc ID 12370 Rev 8
Syntax
nop
ld A, #$55
ld A, $55
ld A, ($55,X)
ld A, ([$55],X)
jrne loop
bset
00..FF
0000..FFFF
00..FF
00..1FE
0000..FFFF
00..FF
0000..FFFF
Destination
byte, #5
00..FF
00..FF
address
Pointer
(hex.)
Example
byte
word
Pointer
(hex.)
size
ST72561-Auto
+ 0
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
Length
(bytes)