ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 181

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
worst case: This occurs when the LIN identifier lasts exactly 10 T
case, the LIN break and synch fields last 49 - 10 = 39T
Assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. This
leads to a maximum allowed header length of:
39 x (1/0.845) T
A margin is provided so that the time-out occurs when the header length is greater than 57
T
occurs.
LIN header length
Even if no timeout occurs on the LIN header, it is possible to have access to the effective LIN
header length (T
the T
This feature is only available when LHDM bit = 1 or when LASE bit = 1.
Mute mode and errors
In mute mode when LHDM bit = 1, if an LHE error occurs during the analysis of the LIN
synch field or if a LIN header time-out occurs then the LHE bit is set but it does not wake up
from mute mode. In this case, the current header analysis is discarded. If needed, the
software has to reset LSF bit. Then the SCI searches for a new LIN header.
In mute mode, if a framing error occurs on a data (which is not a break), it is discarded and
the FE bit is not set.
When LHDM bit = 1, any LIN header which respects the following conditions causes a wake-
up from mute mode:
●
●
●
●
Figure 83. LIN synch field measurement
BIT_SLAVE
A valid LIN break field (at least 11 dominant bits followed by a recessive bit)
A valid LIN synch field (without deviation error)
A LIN identifier field without framing error. Note that a LIN parity error on the LIN
identifier field does not prevent wake-up from mute mode.
No LIN header time-out should occur during header reception.
FRAME_MAX
SM = Synch Measurement Register (15 bits)
t
t
BR
CPU
periods. If it is less than or equal to 57 T
LIN Synch Break
= Baud Rate period
= CPU period
BIT_MASTER
HEADER
condition given by the LIN protocol.
) through the LHL register. This allows monitoring at software level
LPR(n)
Extra
’1’
+ 10T
LINSCI serial communication interface (LIN master/slave)
Doc ID 12370 Rev 8
t
Start
BR
Bit
t
LPR = t
BR
BIT_MASTER
= 16.LP.t
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Measurement = 8.T
BR
/ (16.t
CPU
= 56.15 T
CPU
LIN Synch Field
) = Rounding (SM / 128)
BIT_SLAVE
BR
BIT_MASTER
BIT_SLAVE
= SM.t
periods, then no timeout
CPU
BIT_MASTER
periods.
Stop
Bit
LPR(n+1)
periods. In this
Next
Start
Bit
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