TMP86xy12MG Toshiba, TMP86xy12MG Datasheet - Page 148

• Manufacturer Part Number: TMP86xy12MG
• Manufacturer: Toshiba

Specifications of TMP86xy12MG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: IGBT
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4.5 to 5.5

SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
INTSIO interrupt
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SO pin
INTSIO interrupt
DBR
SCK pin
(Input)
SO pin
DBR
Figure 12-8 Transfer Mode (Example: 8bit, 1word transfer, External clock)
That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF>
is cleared to “0” when a transfer is completed.
“0”.
data; If SIOCR1<SIOS> is not cleared before shift out, dummy data will be transmitted and the operation will
end.
SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to “0”.
Figure 12-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock)
SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted.
When SIOCR1<SIOINH> is set, the transmission is immediately ended and SIOSR<SIOF> is cleared to
When an external clock is used, it is also necessary to clear SIOCR1<SIOS> to “0” before shifting the next
If it is necessary to change the number of words, SIOCR1<SIOS> should be cleared to “0”, then
Write
Write
(a)
(a)
a
a
Write
Write
a
(b)
a
(b)
0
0
b
b
a
a
1
1
a
a
2
2
a
a
3
3
a
a
4
4
a
a
5
5
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a
a
6
6
a
a
7
7
b
b
0
0
b
b
1
1
b
Clear SIOS
b
2
2
Clear SIOS
b
b
3
3
b
b
4
4
b
b
5
5
b
b
TMP86CH12MG
6
6
b
b
7
7