TMP86xy12MG Toshiba, TMP86xy12MG Datasheet - Page 52

• Manufacturer Part Number: TMP86xy12MG
• Manufacturer: Toshiba

Specifications of TMP86xy12MG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: IGBT
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4.5 to 5.5

3.7 External Interrupts
(Pulse inputs of less than a certain time are eliminated as noise).
rupt input pin or an input/output port, and is configured as an input port during reset.
control register (EINTCR).
The TMP86CH12MG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits
Edge selection is also possible with INT1 to INT4. The
Edge selection, noise reject control and
Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "sig-
Note 2: When INT0EN = "0", IL6 is not set even if a falling edge is detected on the
Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an inter-
Source
INT0
INT1
INT2
INT3
INT4
INT5
nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch.
rupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such
as disabling the interrupt enable flag.
INT1
INT2
INT3
INT4
INT0
INT5
Pin
IMF EF6 INT0EN=1
IMF EF8 = 1
IMF EF10 = 1
IMF EF17 = 1
IMF EF22 = 1
IMF EF28 = 1
Enable Conditions
INT0
/P31 pin function selection are performed by the external interrupt
Falling edge
Falling edge
or
Rising edge
Falling edge
or
Rising edge
Falling edge
or
Rising edge
Falling edge,
Rising edge,
Falling and Rising edge
or
H level
Falling edge
Release Edge (level)
Page 41
INT0
/P31 pin can be configured as either an external inter-
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
Pulses of less than 15/fc or 63/fc [s] are elimi-
nated as noise. Pulses of 49/fc or 193/fc [s] or
more are considered to be signals. In the SLOW
or the SLEEP mode, pulses of less than 1/fs [s]
are eliminated as noise. Pulses of 3.5/fs [s] or
more are considered to be signals.
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
INT0
pin input.
Digital Noise Reject
TMP86CH12MG