TMP86xy12MG Toshiba, TMP86xy12MG Datasheet - Page 84

• Manufacturer Part Number: TMP86xy12MG
• Manufacturer: Toshiba

Specifications of TMP86xy12MG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: IGBT
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4.5 to 5.5

Dead Time 1 Setup Register
Pulse Width 1 Setup Register
Period Setup Register
TC7DRA
(0009H, 0008H) Read/Write (Initial value: **** **00 0000 0000)
TC7DRB
(000BH, 000AH) Read/Write (Initial value: **** **00 0000 0000)
TC7DRC
(000DH, 000CH) Read/Write (Initial value: **** **00 0000 0000)
Note 1: The TC7CR1 and TC7CR2 registers should not be rewritten after a timer start (when TC7ST, bit0 of the TC7CR3, is set to
Note 2: Before attempting to modify the TC7CR1 or TC7CR2, clear TC7ST and then check that CNTBF = 0 to determine that the
Note 3: The TC7ST bit only causes the timer to start or stop; it does not indicate the current operating state of the counter. Its
Note 4: In command start and capture mode or command start and trigger start mode, writing 1 to TC7ST causes the timer to
Note 5: TC7CR2<EMGR> is always read as 0 even after 1 is written.
Note 6: Data registers are not updated by merely modifying the output mode with TC7CR2<TC7OUT>. After modifying the output
TC7ST
STM
CSIDIS
CNTBF
EMGF
1).
timer is stopped.
value does not change automatically when counting starts or stops
restart immediately. It means that rewriting any bit other than TC7ST in the TC7CR3 after a command start causes the
rewriting of TC7ST, resulting in the timer being restarted (PPG output is started from the initial state). When TC7ST is set
to 1, rewriting the TC7CR3 (Using a bit manipulation or LD instruction) clears the counter and restarts the timer.
mode, reconfigure data registers TC7DRA to TC7DRE. Ensure that the data registers are written in an appropriate order
because they are not enabled until the upper byte of the TC7DRC is written.
Start/stop the timer.
Select the state when stopped.
Select continuous or one-time output.
Disable the first interrupt at upon a com-
mand start.
Counting status flag
Emergency output stop flag
15
15
15
14
14
14
13
13
13
12
12
12
11
11
11
10
10
10
0: Stop
1: Start
00: Immediately stop and clear the counter with the
01: Immediately stop and clear the counter with the
10: Stop the counter after completing output in the
11: -
0: Allow a periodic interrupt (INTTC7P) to occur in the first period upon a
1: Do not allow a periodic interrupt (INTTC7P) to occur in the first period
0: Counting stopped
1: Counting in progress
0: Operating normally
1: Output stopped in emergency
Page 73
command start.
upon a command start.
TC7DRAH
TC7DRBH
TC7DRCH
output initialized.
output maintained.
current period.
9
9
9
(000DH)
(0009H)
(000BH)
8
8
8
7
7
7
TC7ST = 0
6
6
6
5
5
5
TC7DRAL
TC7DRBL
TC7DRCL
4
4
4
(000CH)
(0008H)
(000AH)
3
3
3
Continuous out-
put
Continuous out-
put
One-time output
–
2
2
2
TC7ST = 1
TMP86CH12MG
1
1
1
0
0
0
Read
R/W
only