TMP86xy12MG Toshiba, TMP86xy12MG Datasheet - Page 85

• Manufacturer Part Number: TMP86xy12MG
• Manufacturer: Toshiba

Specifications of TMP86xy12MG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: IGBT
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4.5 to 5.5

9.2 Control
Dead Time 2 Setup Register
Pulse Width 2 Setup Register
Rising-edge Capture Value Register
Falling-edge Capture Value Register
TC7DRD
(0FB1H, 0FB0H) Read/Write (Initial value: **** **00 0000 0000)
TC7DRE
(0FB3H, 0FB2H) Read/Write (Initial value: **** **00 0000 0000)
TC7CAPA
(0FB5H, 0FB4H) Read only (Initial value: 0000 00** **** ****)
TC7CAPB
(0FB7H, 0FB6H) Read only (Initial value: 0000 00** **** ****)
Note 1: Data registers TC7DRA to TC7DRE have double-stage configuration, consisting of a data register that stores data written
Note 2: When writing data to data registers TC7DRA to TC7DRE, first write the lower byte and then the upper byte.
Note 3: Unused bits (Bits 10 to 15) in the upper bytes of data registers TC7DRA to TC7DRE are not assigned specific register
Note 4: Values read from data registers TC7DRA to TC7DRE may differ from the actual PPG output waveforms due to their dou-
Note 5: Data registers are not updated by merely modifying the output mode with TC7CR2<TC7OUT>. After modifying the output
Note 1: Capture registers (TC7CAPA and TC7CAPB) must be read in the following order: Lower byte of the TC7CAPA, upper byte
Note 2: The next captured data is not updated by reading the TC7CAPA only. The TC7CAPB must also be read.
Note 3: It is possible to read the TC7CAPB only. Read the lower byte first.
Note 4: If a capture edge is not detected within a period, the previous capture value is maintained in the next period.
Note 5: If more than one capture edge is detected within a period, the capture value for the edge detected last is valid in the next
Note 6: Bits 10 to 15 of the TC7CAPA and TC7CAPB are always read as 0.
by an instruction and a compare register to be compared with the counter.
functions. These bits are always read as 0 even when a 1 is written.
ble-stage configuration.
mode, reconfigure data registers TC7DRA to TC7DRE. Ensure that the data registers are written in an appropriate order
because they are not enabled until the upper byte of the TC7DRC is written.
of the TC7CAPA, lower byte of the TC7CAPB, upper byte of the TC7CAPB.
period.
15
15
15
15
14
14
14
14
13
13
13
13
12
12
12
12
11
11
11
11
10
10
10
10
Page 74
TC7CAPAH
TC7CAPBH
TC7DRDH
TC7DREH
9
9
9
9
(0FB1H)
(0FB3H)
(0FB5H)
(0FB7H)
8
8
8
8
7
7
7
7
6
6
6
6
5
5
5
5
TC7CAPBL
TC7CAPAL
TC7DRDL
TC7DREL
4
4
4
4
(0FB0H)
(0FB2H)
(0FB4H)
(0FB6H)
3
3
3
3
2
2
2
2
TMP86CH12MG
1
1
1
1
0
0
0
0