N25Q128 Numonyx, N25Q128 Datasheet - Page 110
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N25Q128
Manufacturer Part Number
N25Q128
Description
128-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase On Boot Sectors, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
Manufacturer
Numonyx
Datasheet
1.N25Q128.pdf
(180 pages)
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9.1.32
9.1.33
110/180
S
C
DQ0
DQ1
S
C
DQ0
DQ1
Figure 39. Write Volatile Configuration Register instruction sequence
Read Volatile Enhanced Configuration Register
The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the
Volatile Configuration Register to be read.
Figure 40. Read Volatile Enhanced Configuration Register instruction sequence
Write Volatile Enhanced Configuration Register
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new
values to be written to the Volatile Enhanced Configuration register. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed. After the
write enable (WREN) instruction has been decoded and executed, the device sets the write
enable latch (WEL). In case of Fast POR, the WREN instruction is not required because a
WREN instruction gets the device out from the Fast POR state (see
POR).
0
High Impedance
1
2
Instruction
3
0
4
1
High Impedance
5
2
Instruction
6
3
7
7
4
8
Configuration Register Out
6
5
9 10 11 12 13 14 15
Volatile Enhanced
5
6
4
MSB
7
MSB
3
7
8
2
6
Volatile Configuration
9 10 11 12 13 14 15
1
5
0
Register In
4
7
Configuration Register Out
3
6
Volatile Enhanced
2
5
1
4
MSB
Section 11.1: Fast
0
3
2
Write_VCR
1
0
Read_VECR
7