N25Q128 Numonyx, N25Q128 Datasheet - Page 118

• Manufacturer Part Number: N25Q128
• Description: 128-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase On Boot Sectors, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

9.2.7
9.2.8
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DQ0
DQ1
C
S
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code, address and input data on the two pins
DQ0 and DQ1, the instruction functionality (as well as the locking OTP method) is exactly
the same as the Program OTP (POTP) instruction of the Extended SPI protocol, please
refer to
Figure 50. Program OTP instruction sequence DIO-SPI
Subsector Erase (SSE)
For devices with bottom or top architecture, at the bottom (or top) of the addressable area
there are 8 boot sectors, each one having 16 4Kbytes subsectors. The Subsector Erase
(SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code and the address on the two pins DQ0 and
DQ1, the instruction functionality is exactly the same as the Subsector Erase (SSE)
instruction of the Extended SPI protocol, please refer to
(SSE)
0
Instruction
1
for further details.
Section 9.1.16: Program OTP instruction (POTP)
2
3
23 21 19 17
22 20 18 16
4
5
6
7
24-Bit Address
15 13 11 9
14 12 10 8
8
9 10 11
12 13 14 15
7
6
5
4
3
2
1
0
16 17 18 19
7
6
Data Byte 1
5
4
Section 9.1.17: Subsector Erase
3
2
for further details.
1
0
20 21 22 23 24 25 26 27
7
6
Data Byte 2
5
4
3
2
1
0
Dual_Program_OTP
7
6
Data Byte n
5
4
3
2
1
0