N25Q128 Numonyx, N25Q128 Datasheet - Page 132

• Manufacturer Part Number: N25Q128
• Description: 128-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase On Boot Sectors, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

9.3.2
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DQ0
DQ3
DQ1
DQ2
S
C
Figure 68. Multiple I/O Read Identification instruction and data-out sequence QIO-
Quad Command Fast Read (QCFR)
The Quad Command Fast Read (QCFR) instruction allows to read the memory in QIO-SPI
protocol, parallelizing the instruction code, the address and the output data on four pins
(DQ0, DQ1, DQ2 and DQ3). The Quad Command Fast Read (QCFR) instruction can be
issued, after the device is set in QIO-SPI mode, by sending to the memory indifferently one
of the 3 instructions codes: 0Bh, 6Bh or EBh, the effect is exactly the same. The 3
instruction codes are all accepted to help the application code porting from Extended SPI
protocol to QIO-SPI protocol.
Apart for the parallelizing on four pins of the instruction code, the Quad Command Fast
Read instruction functionality is exactly the same as the Quad I/O Fast Read of the
Extended SPI protocol, please refer to
SPI
AFh
0
1
5
MAN.
code
4
6
7
2
1
0
2
3
3
5
4
6
7
DEV.
code
4
1
0
2
3
5
Section 9.1.7: Quad I/O Fast Read
5
4
6
7
SIZE
code
6
1
0
2
3
7
8
9 10 11 12 13 14 15
Quad_Multi_Read_IO
for further details.