P60ARM-B/IG/GP1Q Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1Q Datasheet - Page 110

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P60ARM-B/IG/GP1Q

Manufacturer Part Number
P60ARM-B/IG/GP1Q
Description
Microprocessor, 32-Bit Data Bus, 30MHz Processor, 100-QFP
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
P60ARM-B
Note:
Note:
106
MCLK
A[31:0]
nRW
nBW,
LOCK
nTRANS
nOPC
nMREQ,
SEQ
MCLK
ALE
A[31:0]
nWAIT , ABE and ALE are all HIGH during the cycle shown.
Tald is the time by which ALE must be driven LOW in order to latch the current address in phase
2. If ALE is driven low after Tald, then a new address may be latched. ABE is high during the cycle
shown.
T
msh
Figure 37: General Timings
Figure 38: Address Timing
T
T
T
T
T
T
T
ale
opch
T
rwh
blh
mdh
msd
ald
ah
T
T
T
T
T
addr
rwd
bld
mdd
opcd

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