P60ARM-B/IG/GP1Q Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1Q Datasheet - Page 19

• Manufacturer Part Number: P60ARM-B/IG/GP1Q
• Description: Microprocessor, 32-Bit Data Bus, 30MHz Processor, 100-QFP
• Manufacturer: Zarlink Semiconductor, Inc.

software which must work out the cause of the abort, make the requested data available, and retry the
aborted instruction. The application program needs no knowledge of the amount of memory available to
it, nor is its state in any way affected by the abort.
3.4.4 Software interrupt
The software interrupt instruction (SWI) is used for getting into Supervisor mode, usually to request a
particular supervisor function. When a SWI is executed, ARM60 performs the following:
(1)
(2)
(3)
To return from a SWI, use MOVS PC,R14_svc. This will restore the PC and CPSR and return to the
instruction following the SWI.
3.4.5 UndeÞned instruction trap
When the ARM60 comes across an instruction which it cannot handle (see Chapter 4.0 Instruction Set ), it
offers it to any coprocessors which may be present. If a coprocessor can perform this instruction but is busy
at that time, ARM60 will wait until the coprocessor is ready or until an interrupt occurs. If no coprocessor
can handle the instruction then ARM60 will take the undefined instruction trap.
The trap may be used for software emulation of a coprocessor in a system which does not have the
coprocessor hardware, or for general purpose instruction set extension by software emulation.
When ARM60 takes the undefined instruction trap it performs the following:
(1)
(2)
(3)
To return from this trap after emulating the failed instruction, use MOVS PC,R14_und. This will restore the
CPSR and return to the instruction following the undefined instruction.
Saves the address of the SWI instruction plus 4 in R14_svc; saves CPSR in SPSR_svc
Forces M[4:0]=10011 (Supervisor mode) and sets the I bit in the CPSR
Forces the PC to fetch the next instruction from address 0x08
Saves the address of the Undefined or coprocessor instruction plus 4 in R14_und; saves CPSR in
SPSR_und.
Forces M[4:0]=11011 (Undefined mode) and sets the I bit in the CPSR
Forces the PC to fetch the next instruction from address 0x04
Programmer's Model
15