P60ARM-B/IG/GP1Q Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1Q Datasheet - Page 114
P60ARM-B/IG/GP1Q
Manufacturer Part Number
P60ARM-B/IG/GP1Q
Description
Microprocessor, 32-Bit Data Bus, 30MHz Processor, 100-QFP
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.P60ARM-BIGGP1Q.pdf
(121 pages)
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P60ARM-B
110
Tckl
Tckh
Tws
Twh
Tale
Tald
Taddr
Tah
Tdbz
Tdbe
Tabz
Tabe
Tde
Tdz
Tdout
Tdoh
Tdis
Tdih
Tabts
Tabth
Trs
Trh
Tirs
Tirm
Trwd
Trwh
Tmsd
Tmsh
Tbld
Tblh
Tmdd
Tmdh
Topcd
Topch
Tcps
Tcph
Tcpms
Tcpi
Tcpih
Tcts
Tcth
Symbol
clock LOW time
clock HIGH time
nWAIT setup to CKr
nWAIT hold from CKf
address latch open
address latch time
CKr to address valid
address hold time
Data bus tristate time from DBE
Data bus enable time from DBE
Address bus disable from ABE
Address bus enable from ABE
Data bus enable from MCLK
Data bus disable from MCLK
data out delay
data out hold
data in setup
data in hold
ABORT setup time
ABORT hold time
RESET Setup time
RESET hold time
interrupt setup
Interrupt non-recognition time
CKr to nRW valid
nRW hold time
CKf to nMREQ & SEQ
nMREQ & SEQ hold time
CKr to nBW & LOCK
nBW & LOCK hold
CKr to nTRANS
nTRANS hold time
CKr to nOPC valid
nOPC hold time
CPA, CPB setup
CPA,CPB hold time
CPA, CPB to nMREQ, SEQ
CKf to nCPI delay
nCPI hold time
Config setup time
Config hold time
Table 30: AC Parameters (units of nS)
Parameter
23
23
3
3
0
6
3
3
3
3
10
3
3
6
5
3
6
6
6
6
3
3
3
3
3
7*
3
3
2
2
Min
P60ARM*
15
1
22
12
13
12
13
10
28
23
26
23
23
16
16
16
Max
16
16
3
3
0
5
3
3
3
3
9
3
2
6
5
3
6
6
4
4
3
3
3
3
3
12
3
3
2
2
Min
P60ARM-B
14
1
20
12
13
12
13
10
22
21
22
21
21
16
16
16
Max
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