P60ARM-B/IG/GP1Q Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1Q Datasheet - Page 80

• Manufacturer Part Number: P60ARM-B/IG/GP1Q
• Description: Microprocessor, 32-Bit Data Bus, 30MHz Processor, 100-QFP
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
An instruction prefetch occurs at the same time as the above operation, and the program counter is
incremented.
When the shift length is specified by a register, an additional datapath cycle occurs before the above
operation to copy the bottom 8 bits of that register into a holding latch in the barrel shifter. The instruction
prefetch will occur during this first cycle, and the operation cycle will be internal (ie will not request
memory). This internal cycle can be merged with the following sequential access by the memory manager
as the address remains stable through both cycles.
The PC may be one or more of the register operands. When it is the destination external bus activity may
be affected. If the result is written to the PC, the contents of the instruction pipeline are invalidated, and the
address for the next instruction prefetch is taken from the ALU rather than the address incrementer. The
instruction pipeline is refilled before any further execution takes place, and during this time exceptions are
locked out, although will be recorded for subsequent action after the pipeline has been refilled.
PSR Transfer operations exhibit the same timing characteristics as the data operations except that the PC is
never used as a source or destination register. The cycle timings are shown below Table 8: Data Operation
Instruction Cycle Operations.
76
normal
dest=pc
shift(Rs)
shift(Rs)
dest=pc
Cycle
1
1
2
3
1
2
1
2
3
4
Table 8: Data Operation Instruction Cycle Operations
Address
pc+12
pc+12
pc+12
pc+12
alu+4
alu+8
alu+4
alu+8
pc+8
pc+8
pc+8
pc+8
alu
alu
nBW
1
1
1
1
1
1
1
1
1
1
nRW
0
0
0
0
0
0
0
0
0
0
(pc+8)
(pc+8)
(alu)
(alu+4)
(alu+4)
(pc+8)
(pc+8)
Data
(alu)
-
-
nMREQ
0
0
0
0
1
0
1
0
0
0
SEQ
1
0
1
1
0
1
0
0
1
1
nOPC
0
0
0
0
0
1
0
1
0
0