P60ARM-B/IG/GP1Q Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1Q Datasheet - Page 30

• Manufacturer Part Number: P60ARM-B/IG/GP1Q
• Description: Microprocessor, 32-Bit Data Bus, 30MHz Processor, 100-QFP
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32,
which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is
the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL
#0, and allow LSR #32 to be specified.
An arithmetic shift right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31
of Rm instead of zeros. This preserves the sign in 2's complement notation. For example, ASR #5 is shown
in Figure 12: Arithmetic Shift Right.
The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm
is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is
therefore all ones or all zeros, according to the value of bit 31 of Rm.
Rotate right (ROR) operations reuse the bits which 'overshoot' in a logical shift right operation by
reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right
operations. For example, ROR #5 is shown in Figure 13: Rotate Right.
26
31
31
0 0 0 0 0
30
Figure 12: Arithmetic Shift Right
Figure 11: Logical Shift Right
value of operand 2
value of operand 2
contents of Rm
contents of Rm
5
5
4
4
carry out
carry out
0
0