P60ARM-B/IG/GP1Q Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1Q Datasheet - Page 49

• Manufacturer Part Number: P60ARM-B/IG/GP1Q
• Description: Microprocessor, 32-Bit Data Bus, 30MHz Processor, 100-QFP
• Manufacturer: Zarlink Semiconductor, Inc.

4.8.5 Use of R15 as the base
R15 shall not be used as the base register in any LDM or STM instruction.
4.8.6 Inclusion of the base in the register list
When write-back is specified, the base is written back at the end of the second cycle of the instruction.
During a STM, the first register is written out at the start of the second cycle. A STM which includes storing
the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas
with the base second or later in the transfer order, will store the modified value. A LDM will always
overwrite the updated base if the base is in the list.
4.8.7 Data Aborts
Some legal addresses may be unacceptable to a memory management system, and the memory manager
can indicate a problem with an address by taking the ABORT signal HIGH. This can happen on any
transfer during a multiple register load or store, and must be recoverable if ARM60 is to be used in a virtual
memory system.
The state of the LATEABT control signal does not affect the behaviour of LDM and STM instructions in the
event of a memory abort exception.
Aborts during STM instructions
If the abort occurs during a store multiple instruction, ARM60 takes little action until the instruction
completes, whereupon it enters the data abort trap. The memory manager is responsible for preventing
erroneous writes to the memory. The only change to the internal state of the processor will be the
modification of the base register if write-back was specified, and this must be reversed by software (and the
cause of the abort resolved) before the instruction may be retried.
Aborts during LDM instructions
When ARM60 detects a data abort during a load multiple instruction, it modifies the operation of the
instruction to ensure that recovery is possible.
(i)
(ii)
The data abort trap is taken when the load multiple has completed, and the system software must undo any
base modification (and resolve the cause of the abort) before restarting the instruction.
4.8.8 Instruction Cycle Times
Normal LDM instructions take nS + 1N + 1I and LDM PC takes (n+1)S + 2N + 1I incremental cycles, where
S,N and I are as defined in section 5.1 Cycle types on page 65.
Overwriting of registers stops when the abort happens. The aborting load will not take place but
earlier ones may have overwritten registers. The PC is always the last register to be written and so
will always be preserved.
The base register is restored, to its modified value if write-back was requested. This ensures
recoverability in the case where the base register is also in the transfer list, and may have been
overwritten before the abort occurred.
Instruction Set - LDM, STM
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