P60ARM-B/IG/GP1Q Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1Q Datasheet - Page 82

• Manufacturer Part Number: P60ARM-B/IG/GP1Q
• Description: Microprocessor, 32-Bit Data Bus, 30MHz Processor, 100-QFP
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
7.4 Load register
The first cycle of a load register instruction performs the address calculation. The data is fetched from
memory during the second cycle, and the base register modification is performed during this cycle (if
required). During the third cycle the data is transferred to the destination register, and external memory is
unused. This third cycle may normally be merged with the following prefetch to form one memory N-cycle.
The cycle timings are shown below in Table 10: Load Register Instruction Cycle Operations.
Either the base or the destination (or both) may be the PC, and the prefetch sequence will be changed if the
PC is affected by the instruction.
The data fetch may abort, and in this case the destination modification is prevented. In addition, if the
processor is configured for Early Abort, the base register write-back is also prevented.
78
dest=pc
normal
Cycle
1
2
3
1
2
3
4
5
Table 10: Load Register Instruction Cycle Operations
pc+8
alu
pc+12
pc+12
pc+8
alu
pc+12
pc’
pc’+4
pc’+8
Address
nBW
b/w
b/w
1
1
1
1
1
1
nRW
0
0
0
0
0
0
0
0
(pc’+4)
(pc+8)
(pc+8)
Data
(alu)
(pc’)
pc’
-
-
nMREQ
0
1
0
0
1
0
0
0
SEQ
0
0
1
0
0
0
1
1
nOPC
0
1
1
0
1
1
0
0