P60ARM-B/IG/GP1Q Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1Q Datasheet - Page 85

• Manufacturer Part Number: P60ARM-B/IG/GP1Q
• Description: Microprocessor, 32-Bit Data Bus, 30MHz Processor, 100-QFP
• Manufacturer: Zarlink Semiconductor, Inc.

7.7 Store multiple registers
Store multiple proceeds very much as load multiple, without the final cycle. The restart problem is much
more straightforward here, as there is no wholesale overwriting of registers to contend with. The cycle
timings are shown in Table 13: Store Multiple Registers Instruction Cycle Operations.
7.8 Data swap
This is similar to the load and store register instructions, but the actual swap takes place in cycles 2 and 3.
In the second cycle, the data is fetched from external memory. In the third cycle, the contents of the source
register are written out to the external memory. The data read in cycle 2 is written into the destination
register during the fourth cycle. The cycle timings are shown below in Table 14: Data Swap Instruction Cycle
Operations.
The LOCK output of ARM60 is driven HIGH for the duration of the swap operation (cycles 2 & 3) to
indicate that both cycles should be allowed to complete without interruption.
The data swapped may be a byte or word quantity (b/w).
The swap operation may be aborted in either the read or write cycle, and in both cases the destination
register will not be affected.
1 register
n registers
(n>1)
Table 13: Store Multiple Registers Instruction Cycle Operations
Cycle
n+1
1
2
1
2
n
•
Address
pc+8
alu
pc+12
pc+8
alu
alu+•
alu+•
alu+•
pc+12
nBW
1
1
1
1
1
1
1
Instruction Cycle Operations
nRW
0
1
0
1
1
1
1
(pc+8)
(pc+8)
Data
Ra
Ra
R•
R•
R•
nMREQ
0
0
0
0
0
0
0
SEQ
0
0
0
1
1
1
0
nOPC
0
1
0
1
1
1
1
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