P60ARM-B/IG/GP1Q Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1Q Datasheet - Page 92

• Manufacturer Part Number: P60ARM-B/IG/GP1Q
• Description: Microprocessor, 32-Bit Data Bus, 30MHz Processor, 100-QFP
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
7.17 Instruction Speed Summary
Due to the pipelined architecture of the CPU, instructions overlap considerably. In a typical cycle one
instruction may be using the data path while the next is being decoded and the one after that is being
fetched. For this reason the following table presents the incremental number of cycles required by an
instruction, rather than the total number of cycles for which the instruction uses part of the processor.
Elapsed time (in cycles) for a routine may be calculated from these figures which are shown in Table 23:
ARM Instruction Speeds. These figures assume that the instruction is actually executed. Unexecuted
instructions take one cycle.
n
m
b
If the condition is not met all instructions take one S cycle. The cycle types (N, S, I and C) are deÞned in
Chapter 5.0 Memory Interface.
88
Data Processing
MSR, MRS
LDR
STR
LDM
STM
SWP
B,BL
SWI, trap
MUL,MLA
CDP
LDC,STC
MRC
MCR
Instruction
is the number of words transferred.
is the number of cycles required by the multiply algorithm, which is determined by the contents of
Rs. Multiplication by any number between 2^(2m-3) and 2^(2m-1)-1
1<m>16. Multiplication by 0 or 1 takes 1S+1I cycles, and multiplication by any number greater than
or equal to 2^(29) takes 1S+16I cycles. The maximum time for any multiply is thus 1S+16I cycles.
is the number of cycles spent in the coprocessor busy-wait loop.
Cycle
1
Table 22: Unexecuted Instruction Cycle Operations
Address
pc+8
pc+12
(n-1)S
(n-1)S
1S
1S
1S
nS
1S
2S
2S
1S
1S
1S
1S
Table 23: ARM Instruction Speeds
Cycle count
nBW
+ 1N
+ 1N
+ 2N
+ 2N
+ 1N
+ 1N
+ 2N
1
2N
+
+
+
+ (b+1)I
nRW
+ 1I
+ 1I
+ 1I
+ bI
0
mI
bI
bI
(pc+8)
Data
+ 1C
+ 1C
nMREQ
+ 1I
+ 1I + 1N if R15 written
+ 1S + 1N if R15 loaded
+ 1S + 1N if R15 loaded
0
SEQ
for SHIFT(Rs)
1
Additional
takes 1S+mI m cycles for
nOPC
0