P60ARM-B/IG/GP1Q Zarlink Semiconductor, Inc., P60ARM-B/IG/GP1Q Datasheet - Page 70

• Manufacturer Part Number: P60ARM-B/IG/GP1Q
• Description: Microprocessor, 32-Bit Data Bus, 30MHz Processor, 100-QFP
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
When an S-cycle follows an N-cycle, the address will always be one word greater than the address used in
the N-cycle. This address (marked ÒaÓ in the above diagram) should be checked to ensure that it is not the
last in the DRAM page before the memory system commits to the S-cycle. If it is at the page end, the S-cycle
cannot be performed in page mode and the memory system will have to perform a full access.
The processor clock must be stretched to match the full access. When an S-cycle follows an I- or C-cycle, the
address will be the same as that used in the I- or C-cycle. This fact may be used to start the DRAM access
during the preceding cycle, which enables the S-cycle to run at page mode speed whilst performing a full
DRAM access. This is shown in Figure 30: Memory Cycle Optimization .
5.2 Byte addressing
The processor address bus gives byte addresses, but instructions are always words (where a word is 4
bytes) and data quantities are usually words. Single data transfers (LDR and STR) can, however, specify
that a byte quantity is required. The nBW control line is used to request a byte from the memory system;
normally it is HIGH, signifying a request for a word quantity, and it goes LOW during phase 2 of the
preceding cycle to request a byte transfer.
When the processor is fetching an instruction from memory, the state of the bottom two address lines A[1:0]
is undefined.
When a byte is requested in a read transfer (LDRB), the memory system can safely ignore that the request
is for a byte quantity and present the whole word.
ARM60 will perform the byte extraction internally. Alternatively, the memory system may activate only the
addressed byte of the memory. This may be desirable in order to save power, or to enable the use of a
common decoding system for both read and write cycles.
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MCLK
A[31:0]
nMREQ
SEQ
nRAS
nCAS
D[31:0]
Figure 29: ARM Memory Cycle Timing
N-cycle
a
a+4
S-cycle
a+8
I-cycle
C-cycle