HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 10

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

863 C ]Y^Y
2.3
u)
2.4
u)
e)
Pin No.
30
31
32
33
34
35
10
11
47
46
45
36
internal pull up
internal pull up
external pull up required
4
5
6
7
8
9
2
1
PCM bus interface signals
Processor interface signals
C4IO
F0IO
STIO1
STIO2
F1_A
F1_B
D0
D1
D2
D3
D4
D5
D6
D7
A0
/WR
R/W
/RD
/DS
/CS
ALE
/WAIT
Pin Name
Output
Input
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
O
I
I
I
I
I
u)
u)
e)
u)
u)
u)
u)
4.096 MHz / 8.192 MHz / 16.384 MHz clock
PCM/GCI/IOM2 bus clock master: output
PCM/GCI/IOM2 bus clock slave: input (reset default)
Frame synchronisation, 8kHz pulse for PCM/GCI/IOM2 bus
frame synchronisation
PCM/GCI/IOM2 bus master: output
PCM/GCI/IOM2 bus slave: input (reset default)
PCM/GCI/IOM2 bus data line I
Slotwise programmable as input or output
PCM/GCI/IOM2 bus data line II
Slotwise programmable as input or output
enable signal for external CODEC A or C2IO clock (bit clock)
Programmable as positive (reset default) or negative pulse.
enable signal for external CODEC B
Programmable as positive (reset default) or negative pulse.
Mode Function
3, 4
3, 4
2, 3
all
all
all
all
all
all
all
all
all
all
2
2
Data bus (bit 0)
Data bus (bit 1)
Data bus (bit 2)
Data bus (bit 3)
Data bus (bit 4)
Data bus (bit 5)
Data bus (bit 6)
Data bus (bit 7)
Write signal from external processor (low active)
Read/Write select (WR='0')
Read signal from external processor (low active)
I/O data strobe
Chip select (low active)
Address latch enable
ALE is also used for mode selection during power on
(see also 1.3 Processor interface mode on page 8).
Wait signal for external processor (low active)
Address bit 0 from external processor
Cologne
Chip