HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 45

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

863 C ]Y^Y
Name
SCTRL_R
SQ_REC
SQ_SEND
CLKDEL
*
The register is not initialized with a '0' after reset. The register should be initialized as follows
before activating the TE/NT state machine:
note!
TE mode: 0Dh .. 0Fh
NT mode: 6Ch
Addr.
33h
34h
34h
37h
Bits
7..2
3..0
6..5
3..0
7..4
3..0
6..4
0
1
4
7
7
r/w Function
w
w
w
w
w
w
w
w
r
r
r
r
B1-channel receive enable
B2-channel receive enable
'0' B-receive bits are forced to '1'
'1' normal operation
unused
NT mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3,
'1' a complete S or Q multiframe has been received
not defined
'1' ready to send a new S or Q multiframe
NT mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4)
not defined
NT: Data sample point. The lower the value the earlier the
The steps are 163ns.
NT mode only
early edge input data shaping
Low pass characteristic of extended bus configurations can be
compensated. The lower the value the earlier input data pulse is
sampled. No compensation means a value of 6 (110b). Step size
is the same as for bits 3-0.
unused
TE mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4)
TE mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3,
TE:
Reading SQ_REC clears this bit.
Writing to SQ_SEND clears this bit.
(0Fh for S/T interface circuitry shown on page 59)
4 bit delay value to adjust the 2 bit time between receive
and transmit direction (see also Figure 14). The delay of
the external S/T-interface circuit can be compensated.
The lower the value the smaller the delay between
receive and transmit direction.
input data is sampled.
bit 0 = Q4)
bit 0 = Q4)
Cologne
Chip