HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 52

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

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6.1.3 Register read access in de-multiplexed Intel mode (mode 3)
Timing diagram 3: Register read access in de-multiplexed Intel mode (mode 3)
t
CLKI
SYMBOL
t
t
t
t
t
t
t
t
t
RD
RDD
RDDH
SA
SAH
WR
WRDSU
WRDH
CYCLE
*
If the same register as in the last register read/write access is accessed the register address write is
not required.
is the CLKI clock period.
hint!
Read Time
/RD Low to Read Data Out Time
/RD High to Data Buffer Turn Off Time
Address to /RD or /WR Low Setup Time
Address Hold Time after /RD or /WR High
Write Time
Write Data Setup Time to /WR High
Write Data Hold Time from /WR High
End of Read Data Cycle to End of Next Read/Write Data Cycle
Time
CHARACTERISTICS
6x t
MIN.
20ns
30ns
10ns
50ns
20ns
50ns
3ns
2ns
CLKI
Cologne
Chip
MAX.
25ns
15ns
–
–
–