HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 4

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

863 C ]Y^Y
6.2
7
7.1
7.2
8
8.1
8.2
9
9.1
9.2
10
10.1
10.2
10.3
11
12
12.1
12.2
12.3
6.1.5
6.1.6
6.2.1
6.2.2
7.1.1
7.1.2
7.1.3
External circuitries........................................................................................................................... 59
State matrices for NT and TE ......................................................................................................... 65
Binary organisation of the frames .................................................................................................. 67
Clock synchronisation...................................................................................................................... 69
HFC-S mini package dimensions.................................................................................................... 72
Sample circuitries............................................................................................................................. 73
PCM/GCI/IOM2 timing................................................................................................................. 56
S/T interface circuitry.................................................................................................................... 59
Oscillator circuitry for S/T clock................................................................................................... 64
S/T interface activation/deactivation layer 1 for finite state matrix for NT .................................. 65
Activation/deactivation layer 1 for finite state matrix for TE ....................................................... 66
S/T frame structure ........................................................................................................................ 67
GCI frame structure ....................................................................................................................... 68
Clock synchronisation in NT-mode........................................................................................... 69
Clock synchronisation in TE-mode ........................................................................................... 70
Multiple HFC-S mini SYNC scheme ........................................................................................ 71
HFC-S mini in mode 2 (Motorola bus) ..................................................................................... 73
HFC-S mini in mode 3 (Intel bus with separated address bus/data bus)................................... 75
HFC-S mini in mode 4 (Intel bus with multiplexed address bus/data bus)............................... 77
Register read access in multiplexed mode (mode 4)............................................................. 54
Register write access in multiplexed mode (mode 4) ........................................................... 55
Master mode.......................................................................................................................... 57
Slave mode ............................................................................................................................ 58
External receiver circuitry..................................................................................................... 59
External wake-up circuitry.................................................................................................... 60
External transmitter circuitry ................................................................................................ 61
Cologne
Chip