HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 51

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

863 C ]Y^Y
t
6.1.2 Register write access in de-multiplexed Motorola mode (mode 2)
Timing diagram 2: Register write access in de-multiplexed Motorola mode (mode 2)
CLKI
SYMBOL
t
t
t
t
t
t
SA
SAH
WR
WRDSU
WRDH
CYCLE
*
If the same register as in the last register read/write access is accessed the register address write is
not required.
*
If the same register as in the last register read/write access is accessed the register address write is
not required.
is the CLKI clock period.
hint!
hint!
Address to /DS Low Setup Time
Address Hold Time after /DS High
Write Time
Write Data Setup Time to /DS High
Write Data Hold Time from /DS High
End of Write Data Cycle to Start of Next Read/Write Data Cycle
Time
CHARACTERISTICS
6x t
MIN.
20ns
20ns
50ns
30ns
10ns
CLKI
Cologne
Chip
MAX.
–
–
–