HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 70

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HFC-Smini

Manufacturer Part Number
HFC-Smini
Description
Manufacturer
Cologne Chip AG
Datasheet
863C ]Y^Y
10.2
Figure 17: Clock synchronisation in TE-mode
The C4IO clock is adjusted in the 31th time slot at the GCI/IOM bus 1..4 times for one half clock cycle.
This can be reduced to one adjustment of a half clock cycle (see MST_MODE1 register). This is useful if
another HFC series ISDN controller is connected as slave in NT mode to the PCM bus.
The SYNC source can be selected by the MST_MODE2 register settings.
Clock synchronisation in TE-mode
Cologne
Chip

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