HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 16

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

863 C ]Y^Y
3.2.1.3 FIFO full condition in send channels
There are two different FIFO full conditions. The first one is met when the FIFO contents comes up to 7
frames. There is no possibility for the HFC-S mini to manage more frames even if the frames are very
small. The driver software must check that there are never more than 7 HDLC frames in a FIFO.
The second limitation is the size of the FIFO (128 bytes each). FIFO full condition can be checked by
reading the F_USAGE register. It shows the actually occupied FIFO space in bytes.
Furthermore a threshold value can be set for all transmit and receive FIFOs in the F_THRES register.
Then the F_FILL register shows an indication for the filling level for each FIFO.
3.2.1.4 Receive Channels (B1, B2, D and PCM receive)
The receive channels receive data from the S/T or PCM bus interface read registers. The data is
converted from HDLC into plain data and sent to the FIFO. The data can then be read via the
microprocessor bus interface.
The HFC-S mini checks the HDLC data coming in. If it finds a flag or more than 5 consecutive 1s it does
not generate any output data. In this case Z1 is not incremented. Proper HDLC data being received is
converted by the HFC-S mini into plain data. After the ending flag of a frame the HFC-S mini checks the
HDLC CRC checksum. If it is correct one byte with all 0s is inserted behind the CRC data in the FIFO
named STAT. This last byte of a frame in the FIFO is different from all 0s if there is no correct CRC
field at the end of the frame.
Figure 4: FIFO Data Organisation
Cologne
Chip