HFC-Smini Cologne Chip AG, HFC-Smini Datasheet - Page 42

• Manufacturer Part Number: HFC-Smini
• Manufacturer: Cologne Chip AG

863 C ]Y^Y
Name
MST_MODE2
F0_CNT_L
F0_CNT_H
C/I
TRxR
MON1_D
MON2_D
Addr.
2Ah
2Bh
16h
18h
19h
28h
29h
Bits
5..4
7..0
7..0
3..0
7..4
5..2
7..0
7..0
1
2
3
6
7
1
6
7
0
0
r/w Function
r/w on read: indication
r/w first monitor byte
r/w second monitor byte
w
w
w
w
w
w
w
r
r
r
r
r
r
r
'1' generate frame signal for OKI
(see also PCM/GCI/IOM2 timing on page 56)
'1' generate frame signal for OKI
(see also PCM/GCI/IOM2 timing on page 56)
select PCM DPLL sync source
'0' S/T receive frame (only in TE mode and state F7)
'1' SYNC_I input 8 kHz
select SYNC_O output
'0' S/T receive frame 8 kHz (only in TE mode and state F7)
'1' SYNC_I is connected to SYNC_O
PCM/GCI/IOM2 slot select for higher data rates
'00'
'01'
'10'
'11'
This bit is only valid if bit 7 is set.
'0' PCM frame time is reduced as selected by bits 3..2 of the
'1' PCM frame time is increased as selected by bits 3..2 of the
'0' normal operation
'1' enable PCM PLL adjust if no sync source is available
F0IO pulse count
16 bit 125µs time counter (low byte)
F0IO pulse count
16 bit 125µs time counter (high byte)
on write: command
unused
'1' Monitor receiver ready (2 monitor bytes have been
'1' Monitor transmitter ready
Writing on MON2_D starts transmisssion and resets this bit.
reserved
STIO2 in
STIO1 in
MST_MODE1 register
MST_MODE1 register
received)
slots 31..0 accessable
slots 63..32 accessable
slots 95..64 accessable
slots 127..96 accessable
TM
TM
codecs on F1_A
codecs on F1_B
Cologne
Chip