MT57V1MH18A Micron Semiconductor Products, Inc., MT57V1MH18A Datasheet

MT57V1MH18A

Manufacturer Part Number

MT57V1MH18A

Description

18Mb DDR SRAM, 2.5V Vdd, Hstl, 2-Word Burst,

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT57V1MH18A.pdf (25 pages)

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18Mb DDR SRAM

2-Word Burst

Features

• Fast cycle times

• Pipelined, double data rate operation

• Single 2.5V ±0.1V power supply (V

• Separate isolated output buffer supply (V

• JEDEC-standard 1.5V to 1.8V (±0.1V) HSTL I/O

• User-selectable trip point with V

• HSTL programmable impedance outputs

• Optional-use echo clocks (CQ and CQ#) for flexible

• JTAG boundary scan

• Fully-static design for reduced-power standby

• Clock-stop capability

• Common data inputs and data outputs

• Low-control ball count

• Internally self-timed, registered LATE WRITE cycles

• Linear burst order with four-tick burst counter

• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

• Full data coherency, providing most current data

NOTE:

18Mb: 2.5V V

MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03

Options

• Clock Cycle Timing

• Configurations

• Operating Temperature Range

• Package

1. A Part Marking Guide for the FBGA devices can be found on

synchronized to optional dual-data clocks

receive data synchronization

package

Micron’s Web

5ns (200 MHz)

6ns (167 MHz)

7.5ns (133 MHz)

1 Meg x 18

512K x 36

Commercial (0°C £ T

165-ball, 13mm x 15mm FBGA

, HSTL, Pipelined DDRb2 SRAM

site—http://www.micron.com/numberguide.

£ 70°C)

REF

MT57V512H36A

MT57V1MH18A

Marking

)

None

-7.5

-5

-6

2.5V V

Table 1:

General Description

high-speed, low-power CMOS designs using an

advanced 6T CMOS process.

advanced synchronous peripheral circuitry and a 2-bit

burst counter. All synchronous inputs pass through

registers controlled by an input clock pair (K and K#)

and are latched on the rising edge of K and K#. The

synchronous inputs include all addresses, all data

inputs, active LOW load (LD#) and read/write (R/W#).

Write data is registered on the rising edges of both K

and K#. Read data is driven on the rising edge of C and

C# if provided, or on the rising edge of K and K#, if C

and C# are not provided.

(ZQ). Synchronous data outputs (Q) are closely

matched to the two echo clocks (CQ and CQ#), which

can be used as data receive clocks. Output data clocks

(C and C#) are also provided for maximum system

clocking and data synchronization flexibility.

MT57V1MH18A

MT57V512H36A

PART NUMBER

MT57V1MH18AF-xx

MT57V512H36AF-xx

, HSTL, PIPELINED DDRb2 SRAM

The Micron

The DDR SRAM integrates an 18Mb SRAM core with

Asynchronous inputs include impedance match

Figure 1: 165-Ball FBGA

Valid Part Numbers

DDR synchronous SRAM employs

1 MEG x 18, 512 x 36

DESCRIPTION

1 Meg x 18, DDRb2 SRAM

512K x 36, DDRb2 SRAM

Related parts for MT57V1MH18A

MT57V1MH18A Summary of contents

Page 1

... A • Package 165-ball, 13mm x 15mm FBGA NOTE Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/numberguide. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD MT57V1MH18A MT57V512H36A ) REF ...

Page 2

... At slower frequencies, the DDR SRAM requires a single 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD NO OPERATION (NOP) cycle when transitioning from a READ to a WRITE cycle. At higher frequencies, a sec- ond NOP cycle may be required to prevent bus conten- tion ...

Page 3

... The user can operate the part with fewer than 1,024 clock cycles, but optimal output impedance is not guaranteed. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD Clocking The approaches. C and C# may be supplied to the SRAM to ...

Page 4

... CQ and CQ# do not tri-state except during some JTAG test modes. 5. For 1 Meg x 18 and a = 18. For 512K x 36 and a = 36. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD Figure 2: Functional Block Diagram 1 Meg x 18; 512K x 36 ...

Page 5

... For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD Figure 3: Application Example R = 250Ω ...

Page 6

... L NC DQ15 DQ16 DQ17 R TDO TCK SA NOTE: 1. Expansion address: 10A for 36Mb 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM R/W# BW1 BW0 SA0 ...

Page 7

... TDO TCK SA NOTE: 1. Expansion address: 3A for 36Mb 2. BW2# controls writes to DQ18:DQ26 3. BW1# controls writes to DQ9:DQ17 4. BW3# controls writes to DQ27:DQ35 5. BW0# controls writes to DQ0:DQ8 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM R/W# K# BW2# BW1# ...

Page 8

... No Connect: These balls are internally connected to the die, but have no function and may be left not connected to board to minimize ball count. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512 HSTL, PIPELINED DDRb2 SRAM DD Q/2. Provides a reference voltage for the input buffers. ...

Page 9

... SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated after burst count = 2. 2. State transitions (LD# = LOW (LD# = HIGH (R/W# = HIGH (R/W# = LOW). 3. State machine control timing sequence is controlled by K. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD Figure 4: Bus Cycle State Diagram ...

Page 10

... This table illustrates operation for x18 devices. The x36 operation is similar except for the addition of BW2# (controls DQ18:DQ26) and BW3# (controls DQ27:DQ35). 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512 HSTL, PIPELINED DDRb2 SRAM DD LD# ...

Page 11

... Notes appear following parameter tables on page 14; 0°C £ T DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to ..... -0.5V to +3.4V SS the device ...

Page 12

... Clock Capacitance Table 12: Thermal Resistance Note 13; notes appear following parameter tables on page 14 DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Balls (Bottom) 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD £ +70° CONDITIONS SYM ³ ³ ...

Page 13

... Data-in valid rising edge Hold Times K rising edge to address hold K rising edge to control inputs hold K, K# rising edge to data-in hold 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD £ +70° SYM MIN MAX ...

Page 14

... DD increases with faster cycle times. I with faster cycle times and greater output loading. Typical value is measured at 6ns cycle time. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM 10. Typical values are measured at V ...

Page 15

... Input rise and fall times . . . . . . . . . . . . . . . . . . . . 0.7ns Input timing reference levels . . . . . . . . . . . . . . . . 0.75V Output reference levels . . . . . . . . . . . . . . . . . . VDDQ/2 ZQ for 50 W impedance . . . . . . . . . . . . . . . . . . . . . 250 W Output load . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 5 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512 HSTL, PIPELINED DDRb2 SRAM DD Output Load Equivalent V REF ...

Page 16

... Outputs are disabled (High-Z) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD Figure 6: READ/WRITE Timing ...

Page 17

... NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. ...

Page 18

... Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512 HSTL, PIPELINED DDRb2 SRAM DD The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to ...

Page 19

... The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1-compliant. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512 HSTL, PIPELINED DDRb2 SRAM DD Note that since the PRELOAD part of the command ...

Page 20

... CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 10. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD Figure 9: TAP Timing ...

Page 21

... This table defines DC values for TAP control and data balls only. The DQ SRAM balls used in the JTAG operation will have the same values as defined in Table 8, “DC Electrical Characteristics and Operating Conditions,” on page 11. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD TAP AC Output Load Equivalent to 2 ...

Page 22

... IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD DESCRIPTION 000 Revision number. def = 010 for 36Mb density def = 001 for 18Mb density def = 000 for 9Mb density for x36 width ...

Page 23

... V , HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512 HSTL, PIPELINED DDRb2 SRAM DD BIT# FBGA BALL 37 10D 10C 40 11D 11B 44 11C ...

Page 24

... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD Figure 11: 165-Ball FBGA C 10 ...

Page 25

... Added AC Electrical Characteristics and Operating Conditions table Rev. A, Pub. 4/02, ADVANCE...........................................................................................................................................4/02 • New ADVANCE data sheet 18Mb: 2. HSTL, Pipelined DDRb2 SRAM DD MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03 2. HSTL, PIPELINED DDRb2 SRAM DD test conditions for read to write ratio DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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