MT57V1MH18A Micron Semiconductor Products, Inc., MT57V1MH18A Datasheet - Page 17

• Manufacturer Part Number: MT57V1MH18A
• Description: 18Mb DDR SRAM, 2.5V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

IEEE 1149.1 Serial Boundary Scan
(JTAG)
access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the
set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are
excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully-compliant TAPs. The TAP operates using
JEDEC-standard 2.5V I/O logic levels.
register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
JTAG feature. To disable the TAP controller, TCK must
be tied LOW (V
TDI and TMS are internally pulled up and may be
unconnected. Alternately, they may be connected to
V
unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the opera-
tion of the device.
NOTE:
18Mb: 2.5V V
MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03
DD
The SRAM incorporates a serial boundary scan test
The SRAM contains a TAP controller, instruction
It is possible to operate the SRAM without using the
The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.
1
0
through a pull-up resistor. TDO should be left
TEST-LOGIC
RUN-TEST/
DD
TAP Controller State Diagram
RESET
IDLE
0
, HSTL, Pipelined DDRb2 SRAM
1
SS
) to prevent clocking of the device.
Figure 7:
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
DR-SCAN
SHIFT-DR
EXIT1-DR
EXIT2-DR
1
SELECT
0
0
1
0
1
1
0
1
1
0
0
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
1
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
SELECT
0
0
1
0
1
1
0
2.5V V
1
1
0
0
17
DD
Test Access Port (TAP)
Test Clock (TCK)
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
Test MODE SELECT (TMS)
controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.
Test Data-In (TDI)
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 7. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most signifi-
cant bit (MSB) of any register, as illustrated in Figure 8.
NOTE:
Test Data-Out (TDO)
out from the registers. The output is active depending
upon the current state of the TAP state machine, as
shown in Figure 7. The output changes on the falling
edge of TCK. TDO is connected to the least significant
bit (LSB) of any register, as depicted in Figure 8.
TMS
TCK
TDI
, HSTL, PIPELINED DDRb2 SRAM
The test clock is used only with the TAP controller.
The TMS input is used to give commands to the TAP
The TDI ball is used to serially input information
X = 106.
The TDO output ball is used to serially clock data-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TAP Controller Block Diagram
Selection
Circuitry
TAP CONTROLLER
1 MEG x 18, 512 x 36
Boundary Scan Register
Figure 8:
31
Identification Register
x
30
Instruction Register
.
29
.
Bypass Register
.
.
.
.
.
.
2
2
2
1
1
1
0
0
0
0
©2003 Micron Technology Inc.
Selection
Circuitry
TDO