MT57V1MH18A Micron Semiconductor Products, Inc., MT57V1MH18A Datasheet - Page 10

• Manufacturer Part Number: MT57V1MH18A
• Description: 18Mb DDR SRAM, 2.5V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 6:
Notes 1-7
Table 7:
Note 7, 8
NOTE:
18Mb: 2.5V V
MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. ­ means rising edge; ¯ means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C
3. R/W# and LD# must meet setup and hold times around the rising edge (LOW to HIGH) of K. All control inputs are
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification. A0 refers to the address input during a WRITE or READ
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by
7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation
8. This table illustrates operation for x18 devices. The x36 operation is similar except for the addition of BW2# (controls
OPERATION
OPERATION
WRITE Cycle:
Load address, input write data on consecutive K and
K# rising edges
READ Cycle:
Load address, read data on consecutive C and C#
rising edges
NOP: No operation
STANDBY: Clock stopped
WRITE D0:17 at K rising edge
WRITE D0:17 at K# rising edge
WRITE D0:8 at K rising edge
WRITE D0:8 at K# rising edge
WRITE D9:17 at K rising edge
WRITE D9:17 at K# rising edge
WRITE nothing at K rising edge
WRITE nothing at K# rising edge
and C# are HIGH, then data outputs are delivered at K and K# rising edges.
registered during the rising edge of K.
cycle. A0 + 1 refers to the next internal burst address in accordance with the burst sequence.
overcoming transmission line charging symmetrically.
provided that the setup and hold requirements are satisfied.
DQ18:DQ26) and BW3# (controls DQ27:DQ35).
DD
, HSTL, Pipelined DDRb2 SRAM
Truth Table
BYTE WRITE Operation
2.5V V
LD#
H
X
L
L
10
DD
R/W#
, HSTL, PIPELINED DDRb2 SRAM
H
X
X
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
L
L
L
L
®
®
®
®
K
H
H
H
H
Stopped
L®H
L®H
L®H
K
1 MEG x 18, 512 x 36
L
L
L
L
®
®
®
®
K#
H
H
H
H
Q
Previous
D
High-Z
OUT
K(t)­
State
C(t)­
IN
DQ
at
at
(A0)
(A0)
BW0#
0
0
0
0
1
1
1
1
©2003 Micron Technology Inc.
Q
D
K#(t + 1)­
OUT
C#(t + 1)­
Previous
IN
High-Z
State
(A0 + 1)
DQ
(A0 + 1)
at
at
BW1#
0
0
1
1
0
0
1
1