MT57V1MH18A Micron Semiconductor Products, Inc., MT57V1MH18A Datasheet - Page 8

• Manufacturer Part Number: MT57V1MH18A
• Description: 18Mb DDR SRAM, 2.5V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 4:
18Mb: 2.5V V
MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03
BW_#
V
R/W#
SYM
TDO
TMS
V
DQ_
CQ#
LD#
SA0
TCK
V
CQ,
TDI
V
ZQ
DD
NC
C#
K#
SA
C
K
REF
DD
SS
Q
DD
, HSTL, Pipelined DDRb2 SRAM
Supply Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for range.
Supply Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. See DC Electrical Characteristics and
Supply Power Supply: GND.
Outpu
Outpu
Outpu
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
–
t
t
t
Ball Descriptions
DESCRIPTION
Synchronous Byte Writes: When LOW, these inputs cause their respective bytes to be registered and
written if W# had initiated a WRITE cycle. These signals must meet setup and hold times around the
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Ball Layout
figures for signal to data relationships.
Output Clock: This clock pair provides a user-controlled means of tuning device output data. The rising
edge of C# is used as the output reference for second output data. The rising edge of C is used as the
output timing reference for first output data. Ideally, C# is 180 degrees out of phase with C. C and C#
may be tied HIGH to force the use of K and K# as the output reference clocks instead of having to
provide C and C# clocks. If tied HIGH, C and C# must remain HIGH and not be toggled during device
operation.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase
with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition
includes address and read/write direction. All transactions operate on a burst of two data (one clock
period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R/
W# is HIGH, WRITE when R/W# is LOW) for the loaded address. R/W# must meet the setup and hold times
around the rising edge of K.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around
the rising edge of K. SA0 is used as the lowest address bit for BURST READ and BURST WRITE operations.
These inputs are ignored when device is deselected or once BURST operation is in progress.
IEEE 1149.1 Clock Input: JEDEC-standard 2.5V I/O levels. This ball must be tied to V
is not used in the circuit.
IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels. These balls may be left as No Connects if the JTAG
function is not used in the circuit.
HSTL Input Reference Voltage: Nominally V
Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. DQ and CQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this ball to
ground. Alternately, this ball can be connected directly to V
mode. This ball cannot be connected directly to GND or left unconnected.
Synchronous Data I/Os: Input data must meet setup and hold times around the rising edges of K and K#.
Output data is synchronized to the respective C and C# data clocks or to K and K# if C and C# are tied
HIGH. See Ball Layout figures for ball site location of individual signals. The x18 devices uses DQ0:DQ17,
and the x36 device uses DQ0:DQ35.
Echo Clocks: The edges of these outputs are tightly matched to the synchronous data outputs and can be
used as data valid indication. These signals run freely and do not stop when Q tri-states.
IEEE 1149.1 Test Output: JEDEC-standard 2.5V I/O level.
Operating Conditions for range.
No Connect: These balls are internally connected to the die, but have no function and may be left not
connected to board to minimize ball count.
2.5V V
8
DD
DD
Q/2. Provides a reference voltage for the input buffers.
, HSTL, PIPELINED DDRb2 SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
Q, which enables the minimum impedance
1 MEG x 18, 512 x 36
SS
if the JTAG function
©2003 Micron Technology Inc.