AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 13

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

MOTOROLA
--
--
--
-- Copyright 1998, by Motorola Inc.
-- All rights reserved.
--
-- Author:
-- Revision: 0.1
-- Date:
-- Notes:
--
--
-------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------------------------
-- TTDEC
------------------------------------------------------------------------------------------------
ENTITY TTDEC is
end; --PORT DEFINITION AND ENTITY
------------------------------------------------------------------------------------------------
ARCHITECTURE BEHAVIOR OF TTDEC is
SIGNAL wflush, wkill, read, rwim
BEGIN
END BEHAVIOR;
------------------------------------------------------------------------------------------------
-- START.VHD
--
-- START() is the portion of the memory controller which decodes incoming
--
--
--
-- Copyright 1998, by Motorola Inc.
-- All rights reserved.
--
-- Author:
-- Revision: 0.3
-- Date:
-- Notes:
--
--
--
-------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
PORT( tt
-- Detect only the following TT types. "tt_take" will be asserted for all cycles we will claim.
--
wflush
wkill
read
rwim
tt_take <= (wflush or wkill or read or rwim);
tt_we_L <= not (wflush or wkill);
-- Needed due to ViewSynthesis bug: optimizes tt1 and tt2 away, then complains about their absence.
monitor <= read;
transfers and decides whether they should be claimed by the controller
or terminated with an error condition.
);
before optimization. ViewSynthesis doesn't seem to care about the NC
input pins at that level.
tt_take
tt_we_L
monitor
<= '1' WHEN (tt(0) = '0' and tt(1) = '0' and tt(2) = '0' and tt(3) = '1' and tt(4) = '0')
ELSE '0';
<= '1' WHEN (tt(0) = '0' and tt(1) = '0' and tt(2) = '1' and tt(3) = '1' and tt(4) = '0')
ELSE '0';
<= '1' WHEN (tt(0) = '0' and tt(1) = '1' and tt(2) = '0' and tt(3) = '1' and tt(4) = '0')
ELSE '0';
<= '1' WHEN (tt(0) = '0' and tt(1) = '1' and tt(2) = '1' and tt(3) = '1' and tt(4) = '0')
ELSE '0';
Gary Milliorn
6/10/98
All logic is active low when appended with a "_L".
Passed speedwave check 6/16/98.
Gary Milliorn
9/23/98
All logic is active low when appended with a "_L".
Passed speedwave check 6/16/98.
Moved ADSC* assertion to state machine.
Freescale Semiconductor, Inc.
For More Information On This Product,
Minimal PowerPC System Design
: in
: buffer std_logic;
: buffer std_logic;
: buffer std_logic
Go to: www.freescale.com
std_logic_vector( 0 to 4 );
: std_logic;
-- current transfer type.
-- asserted when TT matches types.
-- asserted when cycle is write.
-- ViewSynthesis bug -- not useful.
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